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d a t a sh eet preliminary speci?cation supersedes data of 1996 sep 27 file under integrated circuits, ic03 1997 mar 07 integrated circuits TEA1401T power plug for the universal mains
1997 mar 07 2 philips semiconductors preliminary speci?cation power plug for the universal mains TEA1401T features designed for compact power plugs supplying up to 20 w integrated high-voltage power dmos fet 625 v/1 a operates from all mains supplies (90 to 280 v ac) major design: current regulation at the primary side (no opto-coupler, no secondary electronics) low external/peripheral component count combines accurate constant-voltage source (for supply) and accurate constant-current source (for charging) in one ic foldback feature requires simple input filter as a result of good emc design overshoot protection (output voltage) protects against under-voltage input, over-current and over-temperature 20-pin so medium-power package. general description the TEA1401T is a self oscillating power supply (sops) controller ic that operates directly from the rectified universal mains. it is implemented in the bcd power logic 750 v process and includes the high voltage power switch making an integrated single-switch flyback converter. dedicated circuitry for high power efficiency is built-in, which makes a slim-line electronic power plug concept possible. the basic function is a galvanically isolated, combined current and voltage source. no electronics are required at the secondary side of the transformer. implementation of the TEA1401T renders a simple, small and accurate battery charger system. the TEA1401T is capable of self starting directly from the high voltage mains line. quick reference data ordering information symbol parameter conditions min. typ. max. unit v 20 output voltage at pin 20 (drain) 20 times -- 625 v i 20 current in mos switch peak value -- 1a f sw operating switching frequency range c cpfm = 470 pf 5 - 150 khz i 1 input current at pin 1 (v in ), from the high input voltage. v at can supply from the low voltage auxiliary winding v at < 10 v (peak) -- 3ma v at > 10 v (peak); f sw = 90 khz - 430 530 m a v at > 10 v (peak); f sw = 150 khz - 560 660 m a i 17 average input current at pin 17 (v at )v at < 10 v (peak) -- 300 m a v at > 10 v (peak) -- 3ma t amb operating ambient temperature - 20 - +85 c type number package name description version TEA1401T so20 plastic small outline package; 20 leads; body width 7.5 mm sot163-1
1997 mar 07 3 philips semiconductors preliminary speci?cation power plug for the universal mains TEA1401T block diagram handbook, full pagewidth mbh570 11 band-gap TEA1401T voltage setting r out compensation low voltage over voltage i ref g out compensation 1/6 g out 7 r i 12 r v t1 auxiliary winding v i j ref j ref j ref/3 1 1 d reset maximum on time temperature protection por supply timing fet turn-off v in from mains rectifier and filter 1 17 v in 14 3 13 v ic c pfm foldback 10 c v 9 mains hard wired r ref v gap v at secondary stroke t1 primary winding t1 secondary winding c y single-shot d-type flip-flop foldback clock tr i top regulator leading edge blanking 20 tp 25 m a i u 8 2, 18, 19 5, 6, 15, 16 n.c. gnd c i s r q q drain output 4 source on q & temp max over temperature minimum track- and- hold peak detector i peak correction current setting limiter out 130 m a 2.5 m a in out 1.2 v 90 mv in r i i g m = fig.1 block diagram.
1997 mar 07 4 philips semiconductors preliminary speci?cation power plug for the universal mains TEA1401T pinning symbol pin description v in 1 input for recti?ed and ?ltered mains voltage for initial powering n.c. 2 not connected c pfm 3 frequency range setting for the pulse frequency modulation source 4 source of internal mos switch gnd1 5 ground 1 gnd2 6 ground 2 r i 7 setting of nominal output current c i 8 frequency compensation of current control loop r ref 9 setting of reference current c v 10 frequency compensation of voltage control loop g out 11 nulling of the output conductance of the current source function r v 12 setting of the nominal output voltage foldback 13 enabling of the foldback feature in the output characteristic v ic 14 buffering of internal supply voltage gnd3 15 ground 3 gnd4 16 ground 4 v at 17 input for voltage and power from auxiliary winding for timing and powering n.c. 18 not connected n.c. 19 not connected drain 20 drain of internal mos switch fig.2 pin configuration. handbook, halfpage TEA1401T mbh571 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v in c pfm r i c i r ref c v source gnd1 gnd2 n.c. drain gnd4 n.c. n.c. v at gnd3 foldback v ic r v g out
1997 mar 07 5 philips semiconductors preliminary speci?cation power plug for the universal mains TEA1401T functional description the TEA1401T is the heart of a compact flyback dc-to-dc converter, with the ic placed at the primary side. an auxiliary primary winding of the transformer is used for indirect feedback to control the isolated output. this extra winding also powers the device. control of the converted power is carried out by current mode control and pulse frequency modulation (pfm), as illustrated in fig.1. the primary current is sensed by a comparator. the frequency is determined by the maximum of the transformer demagnetizing time and the time of the voltage controlled monostable multivibrator (single-shot). the TEA1401T senses signals at the primary side of the transformer to reconstruct the current and voltage which are present at the secondary side. comparison of these reconstructions with the internal reference leads to adaptation of the turn-off current level for the primary switch and also to adaptation of the single-shot time. current control (see fig.3) the current through the main switch is measured by the peak detector shown in fig.1. the timing block generates a signal secondary stroke which is logic 1 when the voltage of the auxiliary winding is negative. the measured peak current, multiplied by the ratio of the resistors connected to pins 4 (source) and 7 (r i ), is integrated by a capacitor during the secondary stroke. in this way a reconstruction is made of the secondary charge transfer. the charge estimation q-pulse (see fig.3) is drawn from the capacitor at pin 8 (c i ) for each pulse. also this capacitor, the charge error memory, is continuously charged with the reference current. in this way the real (reconstructed) current is compared with the reference yielding the voltage v ci at pin 8. the v ci level provides the turn-off current level for the main switch and the single-shot time. input from the voltage part of the loop is used to improve the current reconstruction, resulting in a lower output conductance of the complete converter. in the block diagram this is denoted as g out compensation. the block i peak correction is able to increase the output from the peak detector to improve line regulation. voltage control the voltage from the auxiliary winding is sensed as a measure of the secondary voltage. during the secondary stroke the auxiliary winding delivers a negative voltage. this voltage is converted into a current by an external resistor at the r v pin between the transformer winding and virtual ground. this current is compared with a reference current. the difference between the reconstructed voltage and the reference is integrated during the secondary stroke by a capacitor on the c v pin. the voltage on the c v pin is transferred, via a track-and-hold circuit, to the connection point of the current and the voltage loop. the track-and-hold output provides the turn-off current level for the main switch and the single-shot time. the track-and-hold circuit itself is present for loop stability. input from the current part of the loop is used to improve the voltage reconstruction, resulting in lower output impedance of the complete converter (analog to the current control). in the block diagram this is denoted as r out compensation. combined control the two loops, i loop and v loop, each request their own turn-off current level for the main switch and single-shot time. the block minimum in the block diagram outputs the lowest value of the two, preventing the output voltage or current from exceeding its nominal value. the output characteristics of the power plug are displayed in fig.4 (with enabled foldback option). optional foldback (see fig.4) the optional foldback feature of the TEA1401T is performed by sensing the voltage of the auxiliary winding at the end of the flyback stroke. it is actually not a voltage, but the current through pin 12 (r v ) that is measured. when this voltage is low, the reference current in the current control loop is set to the low level j ref /3. the steep foldback enables a turn-down of the converter by short-circuiting the output on the secondary side, for example by a switch-transistor.
1997 mar 07 6 philips semiconductors preliminary speci?cation power plug for the universal mains TEA1401T overshoot protection sensing the voltage during the previously mentioned flyback stroke is also used to signal a voltage overshoot. a voltage overshoot will delay and minimize the next active stroke. this is achieved by discharging the capacitor in the track-and-hold circuit (see fig.1). in this way the power level of the converter is turned down to its minimum immediately in case of a voltage overshoot. minimum output power under no-load condition an additional external pre-load resistor (or zener diode) is necessary to keep the output voltage at its nominal value (or at the zener diode voltage). this is due to the fact that under no-load condition and also at voltage overshoot the converter will keep operating instead of being switched off. although the converter then will operate with a short active stroke and a low frequency, energy is still being converted to the output. to prevent excessive output voltage this energy has to be dissipated. the advantage of a pre-load resistor over a zener diode is that the converter will stay in regulation, maintaining its fast response to load variations. duty cycle control the momentary power level required by the i/v control loop is achieved by controlling the duty cycle of the converter by two actions. first the peak value of the primary current is controlled using a cycle-by-cycle current control. secondly the pulse frequency is modulated. there is a broad region in which both regulation principles are active simultaneously. both controls have a minimum and a maximum value which are set by the resistor on the source pin and the capacitor on the c pfm pin. sops and pfm the switching frequency f sw is set by the transformer demagnetizing time or the frequency control block within the ic (block single-shot in fig.1). at a high power level the transformer determines the frequency. this mode of operation is called self oscillating power supply (sops), and provides maximum efficiency (for a non-continuous conducting flyback converter). in sops the next primary stroke is started right after the previous secondary stroke has ended. timing information is collected from the auxiliary winding. the sops frequency will increase when the power level decreases. the frequency however is limited by the pfm controller (single-shot). when the pfm controller takes over, the frequency will be proportional to the required power level. thus the frequency is reduced when the power level decreases. in pfm there is a variable dead time after the secondary stroke. the next primary stroke is started after the single-shot time has ended. supply initially the ic is powered by a high dc input voltage at pin 1 (v in ). in operation the auxiliary winding takes over. in the event that the auxiliary winding delivers insufficient power for the internal circuitry of the ic, this deficit is supplemented again via pin 1 (v in ). the supply voltage for the internal circuitry is buffered with an external capacitor at pin 14 (v ic ). when the auxiliary winding powers the ic, energy is stored during the active stroke. the rest of the time energy is supplied by the buffer capacitor. protections the ic has a cycle-by-cycle current regulation, with a built-in setting for the absolute maximum voltage across the current sense resistor. also a maximum time is set for the duration of the active stroke. a provision for temperature shut down has been implemented.
1997 mar 07 7 philips semiconductors preliminary speci?cation power plug for the universal mains TEA1401T fig.3 reconstruction of secondary charge transfer. handbook, halfpage mbh580 v auxiliary ( - v secondary ) t t i primary x n q pulse' q pulse i secondary fig.4 v/i ideal characteristics. handbook, halfpage v out (v) v nominal 0 mbh575 i foldback i nominal i out (a)
1997 mar 07 8 philips semiconductors preliminary speci?cation power plug for the universal mains TEA1401T limiting values in accordance with the absolute maximum rating system (iec 134). all voltages are measured with respect to ground; positive currents ?ow into the chip; pins 7, 9, 11 and 12 are not allowed to be voltage driven. the voltage ratings are valid provided other ratings are not being violated; current ratings are valid provided the maximum power rating is not violated. quality specification according to snw-fq-611e . this specification can be found in the quality reference handbook . the handbook can be ordered using the code 9397 750 00192. handling every pin withstands the esd test in accordance with the human body model except for pins v in and drain of which the performance is: pin v in : 1000 v in accordance with the human body model pin drain: 1500 v in accordance with the human body model. symbol parameter conditions min. max. unit voltages v 1 pin 1 (v in ) continuous - 0.4 +400 v v 3 pin 3 (c pfm ) - 0.4 - v v 4 pin 4 (source) - 0.4 +2 v v 8 pin 8 (c i ) - 0.4 - v v 10 pin 10 (c v ) - 0.4 - v v 13 pin 13 (foldback) - 0.4 v ic + 0.4 v v 14 pin 14 (v ic ) -- v v 17 pin 17 (v at ) - 20 +60 v v 20 pin 20 (drain) continuous - +550 v currents i 3 pin 3 (c pfm ) - 0.2 ma i 4 pin 4 (source) - 1+1a i 7 pin 7 (r i ) - 0.2 0 ma i 9 pin 9 (r ref ) - 0.2 0 ma i 11 pin 11 (g out ) - 0.2 0 ma i 12 pin 12 (r v ) - 0.2 0 ma i 14 pin 14 (v ic ) - 300 +1 ma i 20 pin 20 (drain) - 1+1a general p tot total power dissipation t amb <50 c - 1.4 w t stg storage temperature - 55 +150 c t amb operating ambient temperature - 20 +85 c t vj virtual junction temperature - 20 +145 c
1997 mar 07 9 philips semiconductors preliminary speci?cation power plug for the universal mains TEA1401T thermal characteristics note 1. pins gnd1, gnd2, gnd3 and gnd4 connected to sufficient copper area on the printed-circuit board. characteristics v in = 330 v; v at = 36 v; r rref =31k w ; t amb =25 c; ic not in current foldback mode; no over-voltage; no over-temperature; unless otherwise speci?ed. all voltages are measured with respect to ground; currents are positive when ?owing into the ic. symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air (1) 65 k/w symbol parameter conditions min. typ. max. unit supply v in input voltage 60 - 400 v input voltage limit 20 times 500 -- v i in input supply current to v ic and gate v at = 3 v 1.7 2.3 2.9 ma i in(gate) input supply current to gate only v at =36v; non-switching 130 230 330 m a v ic regulated supply voltage at v ic v at = 3 v 6.7 7.2 7.7 v v at = 36 v 7.2 7.9 8.6 v d v ic / d r o voltage decrease at v ic due to its output impedance v at =20v; i vic =0to - 100 ma -- 200 mv v por power-on reset voltage level, with respect to regulated v ic - 0.7 - 0.5 - 0.1 v i li(vat) leakage current into pin v at v at =6v -- 2 m a v vat v at input voltage - 20 - +60 v i vat v at input current v at = 70 v; i vic =0ma111417ma pulse peak modulator v source(max) maximum peak voltage at pin source v cv =v ci =4v; 1.09 1.19 1.29 v v cv =v ci =4v; 1.05 1.15 1.25 v v source(min) minimum peak voltage at pin source v cv =v ci =0v; t on >t on(min) 75 95 120 mv d v cv-source level shift voltage v ci to v source v cv =4v - 2 - v d v ci-source level shift voltage v cv to v source v ci =4v - 2 - v t on(min) minimum on-time (the minimum time duration of the active stroke) v-mode 490 550 610 ns i-mode 675 750 825 ns dv source dt -------------------------- - 1v/ m s = dv source dt -------------------------- - 0.1 v/ m s =
1997 mar 07 10 philips semiconductors preliminary speci?cation power plug for the universal mains TEA1401T pulse (maximum) frequency modulator r discharge discharge resistance to ground v cpfm = 1.0 v 0.3 0.6 0.9 k w i charge(min) minimum charge current v cv =v ci =0v - 2.5 -m a i charge(max) maximum charge current v cv =v ci =4v - 130 -m a i charge(?x) ?xed charge current active stroke - 25 -m a g transferci transfer from pin c i to pin c pfm v ci = 2.1 to 3.1 v -- 104 -m a/v g transfercv transfer from pin c v to pin c pfm v cv = 2.1 to 3.1 v -- 104 -m a/v v sw(high) high switching voltage level at pin c pfm - 1.0 - v v sw(low) low switching voltage level at pin c pfm dc at pin c pfm - 0.17 - v v ton(max) maximum on-time t on(max) switching voltage level at pin c pfm - 0.54 - v d f pfm frequency spread of the internal oscillator; ; v ci =v cv = 2.1 to 3.1 v 93 104 115 m a/v 2 d t on(max) spread of t on(max) ; v ci =v cv =4v; v source <1v 19 22 25 v/ma sops v demag demagnetization recognition voltage level - 250 - 130 - 10 mv current regulation v i(pkc) v peak -i converter input voltage 0.6 - 1.4 v v i(pkc)(slope) v peak -i converter input voltage slope 0.1 - 1.0 v/ m s v pkc(offset) v peak -i converter systematic offset -- 13 - mv i transfer(ri-ci) r i to c i current transfer i gout =0 -- 0.99 - a/a i transfer(gout-ci) g out to c i current transfer i ri =0 - 0.17 - a/a i peakcor current through sense capacitor in block i peak correction (see fig.1); sunk by pin foldback under test conditions: in lasting active stroke 71013 m a i chain(ci) c i chain error current - 3.3 - 1.0 +1.3 m a i ctrl(error) current control total measured error - 5 - +5 % symbol parameter conditions min. typ. max. unit g transferci v sw(high) ------------------------ g transfercv v sw(high) ------------------------- - v ton(max) i charge(fix) ---------------------- - dv source dt -------------------------- - 0.1 v/ m s >
1997 mar 07 11 philips semiconductors preliminary speci?cation power plug for the universal mains TEA1401T voltage regulation i transfer(rv-cv) r v to c v current transfer v ri < 0.5 v -- 1.00 - a/a v thres(ri) r out converter voltage threshold at pin r i - 0.65 - v g m(rout) r out converter transconductance i cv /v ri v ri > 0.7 v - 4.4 -m a/v i chain(cv) c v chain error current i cv measurement, analogue to that of i chain(ci) - 1.2 0 +1.2 m a v ctrl(error) total error of voltage control loop in ic - 4 - +4 % current foldback; foldback (pin 13) connected to v ic (pin 14) i rv /i rref current ratio discrimination level 0.05 0.1 0.2 a/a i ci(foldback) /i ci(normal) current ratio 0.26 0.33 0.4 a/a voltage overshoot i rv /i rref current ratio discrimination level 1.1 1.2 1.3 a/a v 4(overshoot) peak voltage at pin 4 at overshoot; t on >t on(min) 75 95 120 mv i charge(overshoot) c pfm charge current at overshoot; v cpfm =1v - 2.5 -m a references v ref r ref reference voltage 1.24 1.28 1.32 v i transfer(rref-ci) r ref to c i current transfer - 0.99 - a/a i transfer(rref-cv) r ref to c v current transfer - 0.99 - a/a output stage i lo drain output leakage current v drain = 550 v -- 100 m a v drain(cont) drain output voltage continuous 0 - 550 v v drain(lim) drain output voltage limit 20 times 625 -- v d v drain-source drain-source voltage drop t amb =25 c; i drain = 500 ma -- 6v t amb = 125 c; i drain = 500 ma -- 11 v t f drain fall time v in = 300 v; no external capacitor at pin drain - 100 - ns temperature protection t prot(max) maximum temperature threshold 132 139 146 c t prot(hyst) hysteresis temperature - 1 - c symbol parameter conditions min. typ. max. unit
1997 mar 07 12 philips semiconductors preliminary speci?cation power plug for the universal mains TEA1401T output characteristics of complete power plug output power maximum switching frequency is approximately 150 khz. internal mos maximum switch current is 0.5 to 1 a. maximum handled power with universal mains is approximately 10 w. accuracy of current regulation the accuracy of the ic itself is 5%. accuracy of the complete converter is approximately 7%, depending on the transformer and other components. accuracy of voltage regulation the voltage loop inside the ic has an accuracy of 4%. accuracy of the complete converter is approximately 7%. voltage overshoot when voltage overshoot is detected (during the secondary stroke), the ic first has to wait until this stroke is finished in the normal way. after that the power level of the converter is set to the minimum level within one cycle. voltage overshoot is triggered at 20% above nominal output voltage. if at the moment that overshoot is detected, the transformer still contains energy; this energy can cause some further increase of the output voltage. in case of a pre-load resistor across the output, the converter keeps the output voltage under static conditions on its nominal value. voltage overshoot will only be a dynamic phenomenon in this situation. when only a zener diode is applied, the zener voltage will appear at the output continuously under no-load conditions. ef?ciency an efficiency of 72 to 75% at maximum output power can be achieved for a complete 8 w converter designed for universal mains. ripple the magnitude of the ripple in output voltage is determined by the duty cycle of the converter, the output current level and the value and electrical series resistance (esr) of the output capacitor. a minimal ripple is obtained in a system designed on a maximum duty cycle of 50% under normal operating conditions and a minimized dead time. ripple is inversely proportional to input and output voltages. input characteristics of complete power plug input voltage the input voltage range comprises the universal ac-mains (90 to 280 v). the input transient voltage must be filtered to a maximum of 450 v.
1997 mar 07 13 philips semiconductors preliminary speci?cation power plug for the universal mains TEA1401T application information a converter with the TEA1401T consists of an input filter, a transformer with a third winding (auxiliary), a secondary diode with a capacitor plus other external components as illustrated in fig.5. the load (user) determines the operating mode of the power plug, current or voltage source. the capacitor at v ic (pin 14) buffers the internal supply voltage of the ic which is powered via v in and/or v at . a sense resistor converts the primary current into a voltage at source (pin 4). the voltage of the auxiliary winding is converted into a current through resistor r rv and fed to pin r v . nominal current and voltage are set by resistors r ri and r rv . output conductance of the current is nullified by resistor r rgout . the band-gap voltage is converted into a reference current by resistor r rref . capacitor c cpfm determines the frequency in non-sops mode. there are two loop capacitors, one for current control (c i ), and the other for voltage control (c v ). the impedance at c v (pin 10) can be made more complex, if required for stability. the secondary diode also protects the power plug against a short-circuited output (during the primary stroke), and must therefore be placed inside the power plug cabinet. a pre-load resistor or a zener diode is required to handle an open output which will cause an excessively high output voltage. this is because the power plug continues operating, provided it is connected to the mains, and thus continuously converts energy to the secondary side, even though it is a low, predefined level. if a zener diode is used, the zener voltage must be selected with care, because the over-voltage protection of the ic should not be blocked. if the zener diode voltage is too close to the nominal output voltage of the converter no voltage overshoot will be detected by the ic, causing increased dissipation in the zener during switching of the load. a complete diagram with preliminary component values is shown in fig.6. more detailed information can be found in the application note an96096 .
1997 mar 07 14 philips semiconductors preliminary speci?cation power plug for the universal mains TEA1401T handbook, full pagewidth mbh573 gnd 13 foldback v ic c vic 4 14 5, 6, 15, 16 c i c ci 8 r i r ri 7 c pfm c cpfm 3 r ref r rref r sense g out r gout 9 source drain power plug 4 20 v in 1 11 c v c cv 10 r v 12 v at v out 17 TEA1401T r rv user v out user mains hard wired c y fig.5 power plug with TEA1401T.
1997 mar 07 15 philips semiconductors preliminary speci?cation power plug for the universal mains TEA1401T handbook, full pagewidth mbh574 gnd 1 m f (10%) 8.2 nf (10%) 10 nf (10%) 470 pf (5%) 13 foldback v ic 4 14 c i 8 r i 7 c pfm 3 r ref r sense g out 9 source drain z1 bzd27c150 d1 byd33j 4 20 l4 l3 l2 l1 mains filter r1 v dc < 450 v (also transient) d2 byd77b v in c f1 rectifier bridge 800 v at 0.5 a c f2 1 11 c v 10 r v 12 v at v out 17 TEA1401T c1 z2 user (1) mains hard wired 10 k w (1%) 30 k w (1%) 2.2 w (1%) 2.2 nf 100 k w (1%) 240 k w (1%) c vic 5, 6, 15, 16 c ci r ri c cpfm r rref r gout c cv r rv c y fig.6 power plug with TEA1401T; completed circuit diagram. (1) optional short-circuit provision based on foldback feature. c1 = 330 m f 16 v 10%; c f1 =c f2 = 6.8 m f 385 v 10%. l1 = inductance filter = 560 m h 10%; l2 = 62 turns 0.14 copper inductance; l3 = 8 turns 0.4 copper inductance; l4 = 8 turns 0.14 copper inductance; core ef16/16/5 gap 130 m . r1 = r fuse =18 w 5% at 0.5 w. z2 = bzv55b12 2% at 0.4 w.
1997 mar 07 16 philips semiconductors preliminary speci?cation power plug for the universal mains TEA1401T package outline unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec eiaj mm inches 2.65 0.30 0.10 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.4 sot163-1 92-11-17 95-01-24 10 20 w m b p detail x z e 11 1 d y 0.25 075e04 ms-013ac pin 1 index 0.10 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.050 1.4 0.055 0.42 0.39 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale x q a a 1 a 2 h e l p q e c l v m a (a ) 3 a so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1
1997 mar 07 17 philips semiconductors preliminary speci?cation power plug for the universal mains TEA1401T soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all so packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1997 mar 07 18 philips semiconductors preliminary speci?cation power plug for the universal mains TEA1401T definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1997 mar 07 19 philips semiconductors preliminary speci?cation power plug for the universal mains TEA1401T notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1997 sca53 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - sp, brazil, tel. +55 11 821 2333, fax. +55 11 829 1849 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2870, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580/xxx france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, mumbai 400 018, tel. +91 22 4938 541, fax. +91 22 4938 722 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 417027/1200/02/pp20 date of release: 1997 mar 07 document order number: 9397 750 01503

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